The present invention relates to wafer testing and particularly to a system providing check-in control in wafer testing.
Certain product families require wafers to be 100% tested before sawing. This “on-wafer” test allows device characterization and assurance of known good die for higher integration level products and die sales. At the end of wafer fabrication, all devices on a wafer undergo a performance test to identify faulty ICs. This provides customers with the ability to receive parts that meet their specifications.
Before wafer testing starts, a check-in process is performed to confirm wafer lot ID and corresponding test recipe. In a conventional wafer testing system, a cassette is delivered to circuit probe (CP) equipment, and lot and equipment IDs are input to a manufacturing executive system (MES) manually. The MES receives the lot and equipment IDs and performs a check-in process accordingly. The check-in process confirms the equipment to perform testing for the wafer lot and generates a list of allowable test recipes for an operator to choose from.
Such conventional wafer testing has two major disadvantages.
First, manual check-in for wafers requires additional manpower expended in inputting data and selecting test recipes.
Furthermore, the process is based on lot ID, providing a lot-based recipe control. The lot-based recipe control cannot meet the needs of smaller orders for various products. Accordingly, wafers in the same lot are processed using the same test recipe. The single recipe limitation places restrictions on test operation, resulting in inefficiency in wafer testing.
Hence, there is a need for a wafer testing control system that addresses the shortcomings of the existing technology.